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MODE Host INT SDI SDO CS SCLK CLKE Hardware EC1 EC2 EC3 RLOOP LLOOP TAOS TPOS TNEG TCLK Control Equalizer Synchronizer Internal Clock Generator Jitter Attenuator Elastic Store Data Latch Receive Monitor Transmit Driver Control MTIP MRING Timing Recovery Data Slicers Constant Impedance Line Driver
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3LQ u i 6\P 0&/. ,i2i ', 'HVFULSWLRQ 0DVWHU &ORFNi $ iieee RU eiiea 0+] FORFN LQSXW XVHG WR JHQHUDWH LQWHUQDO FORFNVi 8SRQ /RVV RI 6LJQDO o/26on 5&/. LV GHULYHG IURP 0&/.i /;7eii= 2QO\a ,I 0&/. LV QRW DSSOLHGn WKLV SLQ VKRXOG EH JURXQGHGi 7UDQVPLW &ORFNi Transmit clock input. TPOS and TNEG are sampled on the falling edge of TCLK. If TCLK is grounded, the output drivers enter a high-Z state, except during Remote Loopback. 7UDQVPLW 3RVLWLYH 'DWDi Input for positive pulse to be transmitted on the twisted-pair line. 7UDQVPLW 1HJDWLYH 'DWDi Input for negative pulse to be transmitted on the twisted-pair line. 0RGH 6HOHFW o/;7eii]oi Setting MODE High puts the LXT300Z in the Host Mode. In the Host Mode, the serial interface is used to control the LXT300Z and determine its status. Setting MODE Low puts the LXT300Z in the Hardware (H/W) mode. In the Hardware Mode, the serial interface is disabled and hard-wired pins are used to control configuration and report status. *URXQG o/;7eii=oi 7LH WR *URXQGi
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3LQ u c ae 6\P 51(* 5326 ,i2i '2 '2 'HVFULSWLRQ 5HFHLYH 1HJDWLYH 'DWDa 5HFHLYH 3RVLWLYH 'DWDi Received data outputs. A signal on RNEG corresponds to receipt of a negative pulse on RTIP and RRING. A signal on RPOS corresponds to receipt of a positive pulse on RTIP and RRING. RNEG and RPOS outputs are Non-Return-to-Zero (NRZ). Both outputs are stable and valid on the rising edge of RCLK. LXT300Z only: In the Host Mode, CLKE determines the clock edge at which these outputs are stable and valid. In the Hardware Mode both outputs are stable and valid on the rising edge of RCLK. 5HFRYHUHG &ORFNi This is the clock recovered from the signal received at RTIP and RRING. &U\VWDO ,QSXWa &U\VWDO 2XWSXW o/;7eii=oi An external crystal operating at four times the bit rate (6.176 MHz for DSX-1, 8.192 MHz for E1 applications with an 18.7 pF load) is required to enable the jitter attenuation function of the LXT300Z. These pins may also be used to disable the jitter attenuator by connecting the XTALIN pin to the positive supply through a resistor, and floating the XTALOUT pin. 5HFHLYH 7HUPLQDWLRQ o/;7eii=oi &RQQHFW WR 59o WKURXJK D i N UHVLVWRUi 1R &RQQHFWLRQ o/;7eii=oi 'ULYHU 3HUIRUPDQFH 0RQLWRUi DPM goes High when the transmit monitor loop (MTIP and MRING) does not detect a signal for 63 2 clock periods. DPM remains High until a signal is detected. /RVV RI 6LJQDOi LOS goes High when 175 consecutive spaces have been detected. LOS returns Low when a mark is detected. 7UDQVPLW 7LSa 7UDQVPLW 5LQJi Differential Driver Outputs. These outputs are designed to drive a 25 load. The transmitter will drive 100 shielded twisted-pair cable through a 1:2 step-up transformer without additional components. To drive 75 coaxial cable, two 2.2 resistors are required in series with the transformer. 7UDQVPLW *URXQGi *URXQG UHWXUQ IRU WKH WUDQVPLW GULYHUV SRZHU VXSSO\ 79oi 7UDQVPLW 3RZHU 6XSSO\i oe 9'& SRZHU VXSSO\ LQSXW IRU WKH WUDQVPLW GULYHUVi 79o PXVW QRW YDU\ IURP 59o E\ PRUH WKDQ `iie 9i 0RQLWRU 7LSa 0RQLWRU 5LQJi 7KHVH SLQV DUH XVHG WR PRQLWRU WKH WLS DQG ULQJ WUDQVPLW RXWSXWVi 7KH WUDQVFHLYHU FDQ EH FRQQHFWHG WR PRQLWRU LWV RZQ RXWSXW RU WKH RXWSXW RI DQRWKHU /;7eii= RU /;7eii= RQ WKH ERDUGi 5HFHLYH 7LSa 5HFHLYH 5LQJi The AMI signal received from the line is applied at these pins. A center-tapped, center-grounded, 2:1 step-up transformer is required on these pins. Data and clock from the signal applied at these pins are recovered and output on the RPOS/RNEG and RCLK pins. 5HFHLYH 3RZHU 6XSSO\i oe 9'& SRZHU VXSSO\ IRU DOO FLUFXLWV H[FHSW WKH WUDQVPLW GULY HUVi o7UDQVPLW GULYHUV DUH VXSSOLHG E\ 79oio 5HFHLYH *URXQGi *URXQG UHWXUQ IRU SRZHU VXSSO\ 59oi
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3LQ u ee 6\P INT ,i2i '2 'HVFULSWLRQ ,QWHUUXSW o+RVW 0RGHoi This LXT300Z Host Mode output goes Low to flag the host processor when LOS or DPM go active. INT is an open-drain output and should be tied to power supply RV+ through a resistor. INT is reset by clearing the respective register bit (LOS and/or DPM). (TXDOL]HU &RQWURO i o+i: 0RGHoi The signal applied at this pin in the LXT300Z Hardware Mode and LXT301Z is used in conjunction with EC2 and EC3 inputs to determine shape and amplitude of AMI output transmit pulses. 6HULDO 'DWD ,Q o+RVW 0RGHoi The serial data input stream is applied to this pin when the LXT300Z operates in the Host Mode. SDI is sampled on the rising edge of SCLK. (TXDOL]HU &RQWURO e o+i: 0RGHoi The signal applied at this pin in the LXT300Z Hardware Mode and LXT301Z is used in conjunction with EC1 and EC3 inputs to determine shape and amplitude of AMI output transmit pulses. 6HULDO 'DWD 2XW o+RVW 0RGHoi The serial data from the on-chip register is output on this pin in the LXT300Z Host Mode. If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is Low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to and when CS is High. (TXDOL]HU &RQWURO e o+i: 0RGHoi The signal applied at this pin in the LXT300Z Hardware Mode and LXT301Z is used in conjunction with EC1 and EC2 inputs to determine shape and amplitude of AMI output transmit pulses. &KLS 6HOHFW o+RVW 0RGHoi This input is used to access the serial interface in the LXT300Z Host Mode. For each read or write operation, CS must transition from High to Low, and remain Low. 5HPRWH /RRSEDFN o+i: 0RGHoi This input controls loopback functions in the LXT300Z Hardware Mode and LXT301Z. Setting RLOOP High enables the Remote Loopback mode. Setting both RLOOP and LLOOP High causes a Reset. 6HULDO &ORFN o+RVW 0RGHoi This clock is used in the LXT300Z Host Mode to write data to or read data from the serial interface registers. /RFDO /RRSEDFN o+i: 0RGHoi This input controls loopback functions in the LXT300Z Hardware Mode and LXT301Z. Setting LLOOP High enables the Local Loopback Mode. &ORFN (GJH o+RVW 0RGHoi Setting CLKE High causes RPOS and RNEG to be valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. When CLKE is Low, RPOS and RNEG are valid on the rising edge of RCLK, and SDO is valid on the falling edge of SCLK. 7UDQVPLW $OO 2QHV o+i: 0RGHoi When High, TAOS causes the LXT300Z (Hardware Mode) and LXT301Z to transmit a continuous stream of marks at the TCLK frequency. Activating TAOS causes TPOS and TNEG inputs to be ignored. TAOS is inhibited during Remote Loopback.
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decoupling circuitry. Isolation between the transmit and receive circuits is provided internally.
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The LXT300Z and LXT301Z are fully integrated PCM transceivers for both 1.544 Mbps (DSX-1) and 2.048 Mbps (E1) applications. Both transceivers allow fullduplex transmission of digital data over existing twistedpair installations. The first page of this data sheet shows a simplified block diagram of the LXT300Z; Figure 2 shows the LXT301Z. The LXT301Z is similar to the LXT300Z, but does not incorporate the Jitter Attenuator and associated Elastic Store, or the serial interface port. The LXT300Z and LXT301Z transceivers each interface with two twisted-pair lines (one twisted-pair for transmit, one twisted-pair for receive) through standard pulse transformers and appropriate resistors.
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Upon power up, the transceiver is held static until the power supply reaches approximately 3 V. Upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the transmit and receive delay lines and lock the Phase Lock Loop to the receive line. A reference clock is required to calibrate the delay lines. The transmitter reference is provided by TCLK. MCLK provides the receiver reference for the LXT301Z. The crystal oscillator provides the receiver reference in the LXT300Z. If the LXT300Z crystal oscillator is grounded, MCLK is used as the receiver reference clock. The transceiver can also be reset from the Host or Hardware Mode. In Host Mode, reset is commanded by simultaneously writing RLOOP and LLOOP to the register. In Hardware Mode, reset is commanded by holding RLOOP and LLOOP High simultaneously for 200 ns. Reset is initiated on the falling edge of the reset request. In either mode, reset clears and sets all registers to 0 and then begins calibration.
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The LXT300Z and LXT301Z are low-power CMOS devices. Each operates from a single +5 V power supply which can be connected externally to both the transmitter and receiver. However, the two inputs must be within .3V of each other, and decoupled to their respective grounds separately. Refer to Application Information for typical )LJXUH ea /;7eii= %ORFN 'LDJUDP
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The transceiver incorporates an advanced Driver Performance Monitor (DPM) in parallel with the TTIP and TRING at the output transformer. The DPM circuitry uses four comparators and a 150 ns pulse discriminator to filter glitches. The DPM output level goes high upon detection of 63 consecutive zeros, and is cleared when a one is detected on the transmit line, or when a reset command is received. The DPM output also goes High to indicate a ground on TTIP or TRING. A ground fault induced DPM flag is automatically cleared when the ground condition is corrected (chip reset is not required).
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In Hardware Mode the transceiver is accessed and controlled through individual pins. With the exception of the INT and CLKE functions, Hardware Mode provides all the functions provided in the Host Mode. In the Hardware Mode RPOS and RNEG outputs are valid on the rising edge of RCLK. The LXT301Z operates in Hardware Mode at all times. LXT300Z Only: To operate in Hardware Mode, MODE must be set Low. Equalizer Control signals (EC1 through EC3) are input on the Interrupt, Serial Data In and Serial Data Out pins. Diagnostic control for Remote Loopback (RLOOP), Local Loopback (LLOOP), and Transmit All Ones (TAOS) modes is provided through the individual pins used to control serial interface timing in the Host Mode. )LJXUH ea eio $0, &RGLQJ
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The LXT300Z and LXT301Z transceivers can be controlled through hard-wired pins (Hardware Mode). Both transceivers can also be commanded to operate in one of several diagnostic modes. LXT300Z Only: The LXT300Z can be controlled by a microprocessor through a serial interface (Host Mode). The mode of operation is set by the MODE pin logic level.
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LXT300Z is shown in the Host Mode with a typical T1/ ESF framer providing the digital interface with the host controller. Both devices are controlled through the serial interface. An LXP600A Clock Adapter (CLAD) provides the 2.048 MHz system backplane clock, locked to the recovered 1.544 MHz clock signal. The power supply inputs are tied to a common bus with appropriate decoupling capacitors installed (68 F on the transmit side, 1.0 F and 0.1 F on the receive side).
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